This invention relates to a method of manufacturing a transistor using hybrid thin and thick film techniques and to a transistor manufactured using the same.
The invention further relates to an active matrix device, especially an active matrix liquid crystal display (AMLCD), comprising a row and column array of active elements wherein each element is associated with such a transistor and connected to corresponding row and column conductors.
For the avoidance of doubt, the abbreviation TFT is used hereafter to denote a thin film transistor in which at last one part of the transistor is manufactured using a thin film technique, i.e., by a method such as chemical or physical vapour deposition, or electrolysis, and so TFT includes a transistor made by a hybrid method using both thin film and thick film deposition.
From JP-A-60-133758, it is known to manufacture a TFT using hybrid thin and thick film methods and, in particular, to print source, gate and drain electrodes having formed the body of the TFT, the semiconductor and insulating layer, by conventional thin film techniques. Similarly, from JP-A-04-136917, it is known to manufacture an active matrix device comprising a row and column array of such TFTs and furthermore to print the row and column conductors. In addition, from JP-A 60-159825, it is known to provide a TFT with a printed, silica insulating layer.
As is well known, the gate insulating layer of a TFT is required to be of sufficient thickness so as to prevent electrical breakdown between the gate electrode and the semiconductor layer. However, manufacturing an insulating layer of sufficient thickness using thin film techniques such a CVD can be time consuming and therefore expensive. The alternative of thick film printing of the insulating layer is quicker and cheaper that using a thin film technique, but provides an insulating layer with a low integrity interface with the semiconductor layer. This can lead to a high density of defect states thus providing a TFT with high pre-threshold slope transfer characteristics and a low mobility.
It is an object of the invention to provide an enhanced method of manufacturing a TFT using hybrid thin and thick film manufacturing techniques, and to provide a TFT manufactured using the same. It is a further object of the invention to provide an active matrix device, especially for an AMLCD, comprising an array of such TFTs.
According to the present invention, there is provided a method of manufacturing a TFT comprising source and drain electrodes joined by a semiconductor channel layer, a gate insulating layer formed from at least two sublayers and a gate electrode. The method comprises the steps of forming the gate insulating layer by depositing a thin film sublayer using a thin film technique; and depositing a printed sublayer by printing, wherein the thin film sublayer is located adjacent the semiconductor channel layer.
Such a method provides a TFT with a gate insulator with a high integrity semiconductor interface as one would normally associate with thin film manufacture, whilst enjoying the advantages of thick film manufacture with respect to time and cost.
The method of the present invention can be used to manufacture a top gate (TG) TFT by depositing the thin film sublayer on the semiconductor channel layer and the printed sublayer over the thin film sublayer. Alternatively, the method of the present invention can be used to manufacture a bottom gate (BG) TFT by printing the printed sublayer over the gate electrode, depositing the thin film sublayer over the printed sublayer, and forming the semiconductor layer on the thin film sublayer.
In a TG TFT, the thin film sublayer is preferably inorganic, e.g. silicon nitride, and the printed sublayer organic, e.g. polyimide. This enhances the overall process compatibility with respect to temperature given that the inorganic thin film sublayer is deposited using a typically high temperature thin film technique such as chemical vapour deposition (CVD) and the organic, printed sublayer is printed after, using a lower temperature direct printing process, i.e. a decreasing temperature profile.
The manufacture of a TG TFT is further enhanced when the gate electrode is also formed by a printing process. Similarly, in a coplanar TG TFT, the source, gate and drain electrodes may each be formed by printing, and preferably, in the same printing step.
In a BG TFT, for the same reasons of process compatibility described above, both the thin film and printed sublayers are preferably inorganic. For example, the printed sublayer may comprise sol gel or cermet (tantalum oxide). Normally, an inorganic printed sublayer will be more stable when exposed to high temperatures associated with CVD deposition of the thin film sublayer than an organic material such as polyimide. In an staggered BG TFT, the source and drain electrodes may be printed, being a final low temperature process step.
In order to reduce the mask count during the manufacture of both TG and BG TFTs according to the present invention, the thin film sublayer deposited by CVD and the semiconductor layer may be patterned at the same time, e.g. by etching.
Further provided in accordance with the present invention is an active matrix device, especially an AMLCD, comprising a row and column array of active elements wherein each element is associated with a TFT according to the present invention, and connected to corresponding row and column conductors.